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PROCESSOR FEATURES
Preliminary Technical Data
Blackfin(R) Embedded Processor ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Selectable ADC High Pass Filter TWI or SPI Interface Programmable Audio Data Interface Modes I2S, Left, Right Justified or Frame Sync 16-/20-/24-/32-bit Word Lengths Master or Slave Clocking Mode Microphone Input and Electret Bias with Side Tone Mixer Audio sample rates 8 kHz, 44.1 kHz or 88.2 kHz at XTI/CODEC_MCLK frequency of either 11.2896 MHz (256 x fS) or 16.9344 MHz (384 x fS) 8 kHz, 32 kHz, 48 kHz or 96 kHz at XTI/CODEC_MCLK frequency of either 12.288 MHz (256 x fS) or 18.432 MHz (384 x fS) DAC 100 dB (A-weighted) signal-to-noise ratio at 3.3 V 95 dB (A-weighted) signal-to-noise ratio at 1.8 V ADC 90 dB (A-weighted) signal-to-noise ratio at 3.3 V 85 dB (A-weighted) signal-to-noise ratio at 1.8 V Low power 8 mW stereo playback (1.8 V all power supplies) 20 mW record and playback (1.8 V all power supplies)) Low supply voltages 1.8 V to 3.6 V analog supply range 1.8 V to 3.6 V digital supply range
Up to 600 MHz high-performance Blackfin processor RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring tbd V to tbd V core VDD with on-chip voltage regulation 1.8 V, 2.5 V, or 3.3 V I/O operation Embedded low power audio CODEC 289-ball MBGA package 132K bytes of on-chip memory External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories Nand flash controller Flexible booting options from external flash, SPI and TWI memory or from SPI, TWI, and UART host devices One-time programmable memory for security Two dual-channel memory DMA controllers Memory management unit providing memory protection See the published ADSP-BF522/ADSP-BF523/ADSPBF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Revision PrD datasheet for additional peripherals
EMBEDDED CODEC FEATURES
Stereo 24-bit A/D and D/A converters Highly efficient headphone amplifier Complete stereo/mono or microphone/line interface Normal and USB modes programmed under software control
WATCHDOG TIMER
OTP ROTARY COUNTER
VOLTAGE REGULATOR
JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS RTC SPORT0
B
L1 INSTRUCTION MEMORY USB L1 DATA MEMORY 16 EXTERNAL ACCESS BUS EXTERNAL PORT FLASH, SDRAM CONTROL
SPORT1 INTERRUPT CONTROLLER UART1 UART0 NFC DMA CONTROLLER DMA EXTERNAL BUS PPI SPI TIMER7-1 TIMER0 BOOT ROM EMAC HOST DMA TWI PORT J PORT H PORT G CODEC PORT F
DMA CORE BUS
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2008 Analog Devices, Inc. All rights reserved.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
TABLE OF CONTENTS
General Description ................................................. 3 CODEC Description ................................................. 3 CODEC Pin Descriptions ........................................ 15 CODEC Operation ................................................. 16 CODEC Resetting ............................................... 16 Clocking ........................................................... 16 Digital Audio Interfaces ....................................... 17 Master and Slave Mode Operation .......................... 21 Audio Data Sampling Rates ................................... 21 Software Control Interface .................................... 24 SPI Mode ....................................................... 24 TWI Mode ..................................................... 25 Power Down Modes ............................................ 25 Register Map ........................................................ 27 Specifications ........................................................ 31 Operating Conditions .......................................... 31 Power Consumption ............................................ 31 Electrical Characteristics ....................................... 32 Package Information ........................................... 33 CODEC Clock Timing ............................................ 34 Digital Audio Interface--Master mode ........................ 35 Digital Audio interface--Slave mode .......................... 36 Blackfin SPI/TWI Interface Timing ............................ 37 Digital Filter Characteristics ..................................... 39 289-Ball Mini-BGA Pinout ....................................... 40 Ordering Guide ..................................................... 44
Preliminary Technical Data
REVISION HISTORY
6/08--Revision PrC: Changes from PrB to PrC Adds extensive description of the CODEC peripheral. 6/07--Revision PrB: Changes from PrA to PrB Corrects SS/PG and VRSEL 289-Ball Mini-BGA Ball Assignment (Alphabetically by Signal) ................................. 51 Corrects SS/PG and VRSEL 289-Ball Mini-BGA Ball Assignment (Numerically by Ball Number) ........................... 52 3/07--Revision PrA: Initial Version
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Preliminary Technical Data GENERAL DESCRIPTION
This document describes the differences between the ADSPBF523C/ADSP-BF525C/ADSP-BF527C and the ADSPBF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSPBF526/ADSP-BF527 standard product. Please refer to the published ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSPBF525/ADSP-BF526/ADSP-BF527 Revision PrD datasheet for general description and specifications. This document only describes the exceptions to that datasheet. The ADSP-BF523C/ADSP-BF525C/ADSP-BF527C adds a low power stereo CODEC with an integrated headphone driver to the standard product. The CODEC is designed for portable MP3 audio/speech players and recorders. The CODEC is also suitable for MD, CD-RW machines and DAT recorders. Stereo line and mono microphone level audio inputs are provided, along with a mute function, programmable line level volume control and a bias voltage output suitable for an electret-type microphone.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
The CODEC uses stereo 24-bit multi-bit sigma delta ADCs and DACs with oversampling digital interpolation and decimation filters. Digital audio input word lengths from 16-bits to 32-bits and sampling rates from 8 kHz to 96 kHz are supported. Stereo audio outputs are buffered for driving headphones from a programmable volume control. Line level outputs are provided along with anti-thump mute and power-up/power-down circuitry. The device is controlled by the ADSP-BF523C/ADSPBF525C/ADSP-BF527C 2-wire (TWI) or 3-wire serial peripheral interface (SPI). The interface provides access to all features including volume controls, mutes, de-emphasis and extensive power management facilities.
CODEC DESCRIPTION
The CODEC in the ADSP-BF523C/ADSP-BF525C/ADSPBF527C is a low power, high quality stereo audio CODEC for portable digital audio application. It features two 24-bit A/D converter channels and two 24-bit D/A converter channels. In normal mode, the XMI/CODEC_MCLK oscillator is set up according to the desired sample rates of the ADC and DAC. For ADC or DAC sampling rates of 8 kHz, 32 kHz, 48 kHz or 96 kHz, CODEC_MCLK frequencies of either 12.288 MHz (256 x fS) or 18.432 MHz (384 x fS) can be used. For ADC or DAC sampling rates of 8 kHz, 44.1 kHz or 88.2 kHz, CODEC_MCLK frequencies of either 11.2896 MHz (256 x fS) or 16.9344 MHz (384 x fS) can be used. In USB mode, the XTI/CODEC_MCLK frequency is only 12 MHz allowing for ADC and DAC sampling rates of 8 kHz, 44.1 kHz or 88.2 kHz. The CODEC can operate with power supplies as low as 1.8 V for the analog port and 1.8 V for the digital port. The maximum voltage is 3.6 V for all power supplies.
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ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
The device is controlled by a TWI or SPI serial interface which provides access to all features including volume controls, mutes and extensive power management facilities.
CSB AVDD CONTROL INTERFACE CSDA CSCL CMODE
Preliminary Technical Data
HPVDD VMID CODEC HPGND
AGND MUTE ATTEN/ MUTE MICBIAS RLINEIN VOLUME MUTE MUTE MIC BOOST MUTE LLINEIN VOLUME MUTE MUX ADC DAC MUTE ROUT MICIN DIGITAL FILTERS LOUT MUX ADC DAC MUTE VOLUME/ MUTE ATTEN/ MUTE OSCPD OSC CLKIN DIVIDER XTI/CODEC_MCLK CLKOUT DIVIDER DACDAT CODEC_CLKOUT DIGITAL AUDIO INTERFACE ADCLRC MUTE HEADPHONE LHPOUT DRIVER VOLUME/ MUTE HEADPHONE RHPOUT DRIVER
DACLRC
XTO
Figure 1. Audio CODEC Block Diagram
CODEC_BCLK
The CODEC is designed specifically for portable audio products. Its features, performance and low power consumption make it ideal for portable MP3 players and portable mini-disc players. The CODEC includes line and microphone inputs to the onboard ADC, line and headphone outputs from the on-board DAC, a crystal oscillator, configurable digital audio interface and a choice of two or three wire control interface. The CODEC includes three low noise inputs--a monaural microphone and left and right stereo lines. Line inputs have +12 dB to -34 dB logarithmic volume level adjustments and mute. The microphone input has -6 dB to +34 dB volume level adjustment. An electret microphone bias level is also available. All the required input filtering is contained within the device with no external components required. The on-board stereo analog-to-digital converter (ADC) uses a high-quality multi-bit high-order oversampling architecture to deliver optimum performance with low power consumption. The output from the ADC is available on the digital audio interface. The ADC includes an optional digital high pass filter to remove unwanted dc components from the audio signal.
The on-board digital-to-analog converter (DAC) accepts digital audio from the digital audio interface. Digital filter de-emphasis at 32 kHz, 44.1 kHz and 48 kHz can be applied to the digital data under software control. The DAC uses a high quality multi-bit high-order oversampling architecture to deliver optimum performance with low power consumption. The DAC outputs, microphone (SIDETONE) and line inputs (BYPASS) are available both at line level and through a headphone amplifier capable of efficiently driving low impedance headphones. The headphone output volume is adjustable in the analog domain over a range of +6 dB to -73 dB and can be muted. The design of the CODEC has given much attention to power consumption without compromising performance. It includes the ability to power off selective parts of the circuitry under software control, thus conserving power. Nine separate power saving modes can be configured under software control including a standby and power-off mode. Special techniques allow the audio to be muted and the device safely placed into standby, sections of the device powered off and volume levels adjusted without any audible clicks, pops or
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ADCDAT
Preliminary Technical Data
zipper noises. Standby and power-off modes may be used dynamically under software control, whenever recording or playing is not required. The device supports a number of different sampling rates including industry standard 8 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz and 96 kHz. Additionally, the device has an ADC and DAC that can operate at different sample rates. There are two unique schemes featured within the programmable sample rates of the CODEC. Normal industry standard 256/384 x fS sampling mode may be used, with the added ability to mix different sampling rates. A special USB mode is also included, where all audio sampling rates can be generated from a 12.00 MHz USB clock. Thus, for example, the ADC can record to the processor at 44.1 kHz and be played back from the CODEC at 8 kHz with no external digital signal processing required. The digital filters used for both record and playback are optimized for each sampling rate used.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
The digitized output is available in a number of audio data formats I2S, Frame Sync Mode (a burst mode in which frame sync plus two data packed words are transmitted), MSB-first, left justified and MSB-first, right justified. The digital audio interface can operate in both master or slave modes. A crystal oscillator is included within the device. The device can generate the master clock or alternatively it can accept an external master clock.
AUDIO SIGNAL PATH
This section describes the signal flow, starting with the inputs, then the ADC/ADC filters, then the DAC filters/DAC, and finally the outputs. Each section shows a diagram describing the circuit inside the CODEC, and a diagram showing the external components that must be connected to the CODEC pins. The external components are all shown together in Figure 2.
Line Inputs
The CODEC provides left and right channel line inputs (RLINEIN and LLINEIN). The inputs are high impedance and low capacitance, thus ideally suited to receiving line level signals from external high-fidelity or audio equipment.
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ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Preliminary Technical Data
3.3 V HPVDD +
5.6 K 5.6 K
1F + 220 pF 3.3 V AVDD + LLINEIN 0.1 HPGND F
10 F
10 F 5.6 K 1F + 0.1 RLINEIN CODEC 1F LOUT + 100 47 K 680 MICBIAS 1F + 47 K MICIN RMIC ROUT + 100 47 K AGND F
5.6 K
220 pF
DACLRC DACDAT AUDIO SERIAL DATA I/F ADCDAT ADCLRC CODEC_BCLK
LHPOUT
220 F + 47 K
3.3 V 3-WIRE INTERFACE 2-WIRE INTERFACE 3-WIRE OR 2-WIRE MPU INTERFACE CMODE CSB CSDA CSCL 10 K
RHPOUT
220 F + 47 K
CODEC_CLKOUT 100
VMID XTI/CODEC_MCLK X1 XTO 0.1 F + 10 F
CP
CP
Figure 2. External Components Diagram
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Preliminary Technical Data
The external components needed to complete the line input application are shown in Figure 3.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Using software control, the gain between the line inputs and the ADC is logarithmically adjustable from +12 dB to -34.5 dB in 1.5 dB steps. The ADC full scale input is 1.0 V(rms) at AVDD = 3.3 volts. Any voltage greater than full scale could overload the ADC and cause distortion. The full scale input tracks directly with AVDD. The gain is independently adjustable on both right and left line inputs. However, by setting the INBOTH bit while programming the volume control, both channels are simultaneously updated with the same value. Use of INBOTH reduces the number of software writes required. The line inputs to the ADC can be muted in the analog domain under software control. The software control registers are shown Table 1.
R1
C2
+ LINEIN
R2 AGND
C1
AGND
AGND
Figure 3. Line Input External Circuit
Microphone Input
MICIN is a high impedance, low capacitance input for connecting a wide range of monophonic microphones with different dynamics and sensitivities. The MICIN includes programmable volume adjustments and a mute function. The scheme is shown in Figure 5. Passive RF and active anti-alias filters are incorporated within the microphone
For interfacing to a typical CD system, it is recommended that the input be scaled to ensure that there is no clipping of the signal. R1 = 5.6 k, R2 = 5.6 k, C1 = 220 pF, C2 = 1 F. R1 and R2 form a resistive divider that attenuates the 2 V(rms) output from a compact disk player to a 1 V(rms) level to avoid overloading the inputs. R2 also provides a discharge path for C2, preventing the input to C2 from charging to an excessive voltage that could damage any connected equipment that is not suitably protected against high voltage. C1 forms an RF low pass filter for increasing the rejection of RF interference picked up on any cables. C2 blocks the dc path between the CODEC and the driving audio equipment. C2 together with the input impedance of the CODEC form a high pass filter. As shown in Figure 4 the line inputs are biased internally through the operational amplifier to VMID. Whenever the line inputs are muted or the device placed in standby mode, the line inputs are kept biased to VMID using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when re-activating the inputs.
LINEIN
12.5 K
TO ADC VMID +
Figure 4. Line Input Internal Circuit
Both line inputs include independent programmable volume level adjustments and ADC input mute. Passive RF and active anti-alias filters are also incorporated within the line inputs to prevent degraded performance due to high frequency aliasing into the audio band. LINMUTE/RINMUTE only mute the input to the ADC, which allows the line input signal to pass to the line output in bypass mode.
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ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Table 1. Line Input Software Control
Register Address Bit Label 000 0000 Left Line In Default Description
Preliminary Technical Data
4:0 LINVOL[4:0] 10111 ( 0 dB ) 7 LINMUTE 1
Left Channel Line Input Volume Control 11111 = +12 dB in 1.5 dB steps down to 00000 = -34.5 dB Left Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute Left to Right Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of LINVOL[4:0] and LINMUTE to RINVOL[4:0] and RINMUTE 0 = Disable Simultaneous Load Right Channel Line Input Volume Control 11111 = +12 dB in 1.5 dB steps down to 00000 = -34.5 dB Right Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute Right to Left Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of RINVOL[4:0] and RINMUTE to LINVOL[4:0] and LINMUTE 0 = Disable Simultaneous Load
8
LRINBOTH
0
000 0001 Right Line In
4:0 RINVOL[4:0] 10111 ( 0 dB ) 7 RINMUTE 1
8
RLINBOTH
0
inputs. These allow a matched interface to the multi-bit oversampling ADC and prevent high frequencies from aliasing into the audio band to degrade performance.
There are two stages of gain made up of two low noise inverting operational amplifiers. The first stage has a nominal gain of G1 = 50 k/10 k = 5. The gain of the stage can be adjusted by adding an external resistor (Rmic) in series with MICIN (see Figure 6 on Page 9). The equation below can be used to calculate the gain versus Rmic. Gain = 50 k/(Rmic + 10 k) Or to calculate the value of Rmic to achieve a given gain: Rmic = (50 k/Gain)-10 k For example adding Rmic = 40 k sets the gain of stage one to 1x (0 dB). For Rmic = 90 k gain = 0.5 (-6 dB) and for Rmic = 0 gain = 5x (14 dB). The internal 50 k and 10 k resistors have a tolerance of 15%. The second stage has 0 dB gain that can be software configured to provide a fixed 20 dB of gain for low sensitivity microphones. The microphone input can therefore be configured with a variable gain of between -6 dB and 14 dB on the first stage, and an additional fixed 0 dB or 20 dB on the second stage. This allows a total gain of -6 dB to 34 dB. To maximize the signal-to-noise ratio, stage 1 and stage 2 gains should be configured so that the maximum signal that the ADC receives is equal to the full scale value. The ADC full scale input is 1.0 V(rms) at AVDD = 3.3 volts. Any voltage greater than full scale could overload the ADC and cause distortion. The full scale input tracks directly with AVDD. The microphone input is biased internally through the operational amplifier to VMID. Whenever the line inputs are muted the MICIN input is kept biased to VMID using special antithump circuitry. This reduces audible clicks that may otherwise be heard when re-activating the input.
50 K 10 K MICIN VMID + TO ADC VMID +
Figure 5. Microphone Input Internal Circuit
Software control for MICIN is shown in Table 2. The microphone mute only mutes the input to the ADC, which allows the microphone input signal to pass to the line output in sidetone mode. Table 2. Microphone Input Software Control
Register Bit Label Address 000 0100 0 Default Description Microphone Input Level Boost 1 = Enable Boost 0 = Disable Boost Microphone Mute to ADC 1 = Enable Mute 0 = Disable Mute
MICBOOST 0
1
MUTEMIC
1
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Preliminary Technical Data
The microphone should be connected to the device as shown in Figure 6.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
ADC
The CODEC uses a multi-bit oversampled sigma-delta ADC. A single channel of the ADC is illustrated in the Figure 8. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise.
FROM MICROPHONE INPUT + ANALOG INTEGRATOR TO ADC DIGITAL FILTERS
MICBIAS
R1 C2 FROM MICROPHONE R2 AGND AGND AGND MULTIPLE BITS INSEL C1 FROM LINE INPUT + RMIC MICIN
-
Figure 6. Microphone Input External Circuit
Recommended component values are C1 = 220 pF (npo ceramic), C2 = 1 F, R1 = 680 , R2 = 47 k. Rmic values depend on the gain setting (see previous discussion). R1 and R2 form part of the biasing network. R1 connected to MICBIAS is necessary only for electret type microphones that require a voltage bias. R2 should always be present to prevent the microphone input from charging to a high voltage which could damage the microphone upon connection. R1 and R2 should be large so as not to attenuate the signal from the microphone, which can have source impedance greater than 2 k. C1 together with the source impedance of the microphone and the input impedance of MICIN forms an RF filter. C2 is a dc blocking capacitor that allows the microphone to be biased at a different dc voltage than the MICIN signal. Microphone Bias The MICBIAS output (shown in Figure 7) provides a low noise reference voltage suitable for biasing electret type microphones. The external resistor biasing network is shown in Figure 6, where MICBIAS is the output of the device (Figure 7). There is a maximum source current capability of 3 mA available for the MICBIAS. This limits the smallest value of external biasing resistors that can safely be used. The MICBIAS output is not active in standby mode.
Figure 8. MultiBit Oversampling Sigma-Delta ADC
The ADC full scale input is 1.0 V(rms) at AVDD = 3.3 volts. Any voltage greater than full scale could overload the ADC and cause distortion. The full scale input tracks directly with AVDD. The device uses a pair of ADCs. The input can be selected by software from either the line inputs or the microphone input. The two channels cannot be selected independently. The control is shown in Table 3. The digital data from the ADC is fed for signal processing to the ADC filters. Table 3. ADC Software Control
Register Bit Label Default Description Address 000 0100 2 INSEL 0 Microphone/Line Input Select 1 = Microphone Input Select 0 = Line Input Select
ADC Filters
The ADC filters perform true 24-bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. Figure 9 illustrates the digital filter path.
VMID
+ MICBIAS R FROM ADC DIGITAL DECIMATOR DIGITAL DECIMATION FILTER TO DIGITAL AUDIO INTERFACE
DIGITAL HPF
HPFEN 2R
Figure 9. ADC Digital Filter
AGND
Figure 7. MICBIAS Internal Circuit
The ADC digital filters contain a digital high pass filter, selectable via software control. There are several types of ADC filters--frequency and phase responses of these are shown in
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ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Digital Filter Characteristics on Page 39. The filter types are automatically configured depending on the sample rate chosen. See USB Mode Sample Rates on Page 23 more details. When the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. By setting HPOR, the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. If the dc offset changes, the stored and subtracted value will not change unless the high-pass filter is enabled. The software control is shown in Table 4. Table 4. ADC Software Control
Register Bit Label Address 000 0101 0 Default Description ADC High Pass Filter Enable 1 = Disable High Pass Filter 0 = Enable High Pass Filter Store DC Offset When High Pass Filter Disabled 1 = Store Offset 0 = Clear Offset
Preliminary Technical Data
DAC
The CODEC uses a multi-bit sigma-delta oversampling digitalto-analog converter as shown in Figure 11.
FROM DAC DIGITAL FILTERS
TO LINE OUTPUT
Figure 11. Multi-bit Oversampling Sigma Delta Schematic
ADCHPD 0
The DAC converts the multi-level digital audio data stream from the DAC digital filters into high quality analog audio.
Line Outputs
The CODEC provides two low impedance line outputs LOUT and ROUT, suitable for driving line loads with 10 k impedance and 50 pF capacitance. The line output is used to selectively sum the outputs from the DAC and/or the line inputs in bypass mode. The LOUT and ROUT outputs are only available at a fixed line output level that is not adjustable in the analog domain. The level is fixed such that at the DAC full scale level the output is 1.0 V(rms) at AVDD = 3.3 volts. The DAC full scale level tracks directly with AVDD. The internal circuit is shown in Figure 12. The line output includes a low order audio low pass filter for removing out-of band components from the sigma-delta DAC. Therefore no further external filtering is required in most applications.
SIDETONE
4
HPOR
0
DAC Filters
The DAC filters perform true 24-bit signal processing to convert the incoming digital audio data from the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by the analog DAC. Figure 10 illustrates the DAC digital filter path.
DIGITAL FROM DIGITAL DE EMPHASIS AUDIO INTERFACE
MUTE
DIGITAL INTERPOLATION FILTER
TO LINE OUTPUTS FROM MICROPHONE INPUT
DEEMP
DACMU
Figure 10. DAC Filter
The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 5. The DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This removes any abrupt step changes in the audio that might otherwise result in audible clicks in the audio outputs. Table 5. DAC Software Control
Register Bit Label Address Default Description De-emphasis Control (Digital) 11 = 48 kHz 10 = 44.1 kHz 01 = 32 kHz 00 = Disable DAC Soft Mute Control (Digital) 1 = Enable Soft Mute 0 = Disable Soft Mute
Rev. PrC |
FROM LINE INPUTS
BYPASS
DACSEL FROM DAC VMID LINEOUT + TO HEADPHONE AMPLIFIER
000 0101 2:1 DEEMP[1:0] 00
Figure 12. Line Output
3
DACMU
1
The DAC output, line input and microphone are summed into the line output. In DAC mode only the output from the DAC is routed to the line outputs. In bypass mode the line input is summed into the line outputs. In sidetone mode the microphone input is summed into the line output. These features can
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Preliminary Technical Data
be used for either over-dubbing, or if the DAC is muted, as a pure analog bypass or sidetone feature that avoids any digital signal processing.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
The internal circuit is shown in Figure 14.
FROM DAC VIA LINEOUT
The line output is muted by either muting the DAC (analog) or soft muting (digital) and disabling the bypass and sidetone paths. See DAC Filters on Page 10 for more information. Whenever the DAC is muted or the device placed in standby mode, the dc voltage is maintained at the line outputs to prevent audible clicks. The software control for the line outputs is shown in Table 6. Table 6. Output Software Control
Register Address 0000100 Bit Label 3 BYPASS Default Description 1 Bypass Switch 1 = Enable Bypass 0 = Disable Bypass DAC Select 1 = Select DAC 0 = Do Not Select DAC Side Tone Switch 1 = Enable Side Tone 0 = Disable Side Tone
HPOUT VMID +
Figure 14. Headphone Amplifier
LHPOUT and RHPOUT volumes can be independently adjusted under software control using the LHPVOL[6:0] and RHPVOL[6:0] bits of the headphone output control registers. The adjustment is logarithmic with an 80 dB range in 1 dB steps from +6 dB to -73 dB. The headphone outputs can be separately muted by writing codes less than 0110000 to the LHPVOL[6:0] or RHPVO[6:0] bits. Whenever the headphone outputs are muted or the device placed in standby mode, the dc voltage is maintained at the line outputs to prevent audible clicks. A zero-cross-detect circuit is provided at the input to the headphones under the control of the LZCEN and RZCEN bits of the headphone output control register. Using these controls, the volume control values are only updated when the input signal to the gain stage is close to the analog ground level. This minimizes audible clicks and zipper noise as the gain values are changed or the device muted. This circuit has no time out, so if dc levels of more than approximately 20 mV are being applied to the gain stage input , the gain will not be updated. This zero-cross function is enabled when the LZCEN or RZCEN bit is set high during a volume register write. If there is concern that a dc level may have blocked a volume change (one made with LZCEN or RZCEN set high) then a subsequent volume write of the same value, but with the LZCEN or RZCEN bit set low will force a volume update, regardless of the dc level. The LHPOUT and RHPOUT volume and zero-cross settings can be changed independently. Or the programmer can lock the two channels together, allowing both to be updated simultaneously. This halves the number of serial writes needed, provided that the gain is the same for both channels. Setting LRHPBOTH while writing to LHPVOL and LZCEN will simultaneously update the right headphone controls. Similarly, setting RLHPBOTH while writing to RHPVOL and RZCEN will simultaneously update the left headphone controls.
4
DACSEL
0
5
SIDETONE
0
The recommended external components are shown in Figure 13 with C1 = 10 F, R1 = 47 k, R2 = 100 .
C1 + LINEOUT
R2
R1 AGND
AGND
Figure 13. Line Outputs External Circuit
C1 forms a dc blocking capacitor to the line outputs. R1 prevents the output voltage from drifting to protect equipment connected to the line output. R2 forms a de-coupling resistor preventing abnormal loads from disturbing the device. Poor choice of dielectric material for C1 can have dramatic effects on the measured signal distortion at the output.
Headphone Amplifier
The CODEC has a stereo headphone output available on LHPOUT and RHPOUT. The output is designed for driving 16 or 32 headphones with maximum efficiency and low power consumption. The headphone output includes a high quality volume level adjustment and mute function.
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ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Software control is shown in Table 7. Table 7. Headphone Output Software Control
Register Bit Label Address Default Description
Preliminary Technical Data
000 0010 6:0 LHPVOL[6:0] 1111001 Left Channel Headphone Output Volume Control ( 0 dB ) +6 dB (1111111) in 1 dB steps down to -73 dB(0110000 ) 0000000 to 0101111 = MUTE 7 LZCEN 0 Left Channel Zero-Cross Detect Enable 1 = Enable 0 = Disable Simultaneous Load of Left Channel Volume, Mute and Zero-Cross Data to Right Channel 1 = Enable Simultaneous Load of LHPVOL[6:0] and LZCEN to RHPVOL[6:0] and RZCEN 0 = Disable Simultaneous Load
8
LRHPBOTH
0
000 0011 6:0 RHPVOL[6:0] 1111001 Right Channel Headphone Output Volume Control ( 0 dB ) +6 dB (1111111) in 1 dB steps down to -73 dB(0110000 ) 0000000 to 0101111 = MUTE 7 RZCEN 0 Right Channel Zero-Cross Detect Enable 1 = Enable 0 = Disable Simultaneous Load of Right Channel Volume, Mute and Zero-Cross Data to Left Channel 1 = Enable Simultaneous Load of RHPVOL[6:0] and RZCEN to LHPVOL[6:0] and LZCEN 0 = Disable Simultaneous Load
8
RLHPBOTH
0
The recommended external components are shown in Figure 15 with C1 = 220 F (10 V electrolytic) and R1 = 47 k.
C1 + HPOUT
R1 AGND
AGND
Figure 15. Headphone Output External Circuit
C1 is a dc blocking capacitor that isolates the dc of the HPOUT from the headphones. R1 is a pull-down resistor that discharges C1 to prevent damage to the headphones.
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June 2008
Preliminary Technical Data
Bypass Mode
The bypass mode routes analog line inputs directly to the analog line and headphone outputs as shown in Figure 16.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
MICIN
12.5 K
-
SIDETONE (OFF)
VMID
+ BYPASS (ON) FROM LINE INPUTS
DACSEL (OFF) FROM DAC VMID LINEOUT +
HPOUT VMID +
Figure 16. Signal Routing in Bypass Mode
Bypass mode is selected under software control using the BYPASS bit as shown in Table 8. In true bypass mode, the output from the DAC (DACSEL) and (SIDETONE) should be deselected from the line output block. However this can also be used to sum the DAC output, line inputs together and microphone inputs. The analog line input and headphone output volume controls and mutes are still operational in bypass mode. The 0 dB gain setting is recommended for the line input volume control to avoid distortion. The maximum signal at any point in the bypass path must be no greater than 1.0 V(rms) at AVDD = 3.3 V. This level tracks directly with AVDD. This means that if the DAC is producing a 1 V(rms) signal, and it is being summed with a 1 V(rms) line BYPASS signal, the resulting LINEOUT signal will be clipped. Table 8. Bypass Mode Software Control
Register Address 000 0100 Bit Label 3 BYPASS Default 1 Description Bypass Switch (analog) 1 = Enable Bypass 0 = Disable Bypass
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June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Sidetone Mode
The sidetone mode routs the microphone input to the line and headphone outputs as shown in Figure 17.
Preliminary Technical Data
MICIN
10 K 50 K
10DB GAIN BOOST -
VMID
+
-
SIDETONE (ON)
VMID
+ BYPASS (OFF) FROM LINE INPUTS
DACSEL (OFF) FROM DAC VMID LINEOUT +
HPOUT VMID +
Figure 17. Sidetone Mode
The sidetone mode allows the microphone input to be attenuated to the outputs for telephone and headset applications. The sidetone mode and attenuation are selected under software control using the SIDETONE bit as shown in Table 9. In true sidetone the output from the DAC (DACSEL) and line inputs (BYPASS) should be deselected from the line output block. However, this can also be used to sum the DAC output, line inputs and microphone inputs together. The microphone boost gain control and headphone output volume control and mutes are still operational in sidetone mode. To avoid distortion the
maximum signal at any point in the sidetone path must be no greater than 1.0 V(rms) at AVDD = 3.3V. This level tracks directly with AVDD. Table 9. Sidetone Mode Control
Register Bit Label Address 000 0100 5 SIDETONE Default Description 0 Sidetone Switch (analog) 1 = Enable Side Tone 0 = Disable Side Tone Sidetone Attenuation 11 = -15 dB 10 = -12 dB 01 = -9 dB 00 = -6 dB
7:6 SIDEATT[1:0] 00
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June 2008
Preliminary Technical Data CODEC PIN DESCRIPTIONS
The ADSP-BF523C/ADSP-BF525C/ADSP-BF527C product adds CODEC signals to those listed in Table 1 of the standard product datasheet ADSP-BF522/523/524/525/526/527 revision PrD. Table 10. CODEC Pin Descriptions
Pin Name CODEC CODEC_CLKOUT CODEC_BCLK DACDAT DACLRC ADCDAT ADCLRC CMODE CSB CSDA CSCL XTI/ CODEC_MCLK XTO LHPOUT RHPOUT LOUT ROUT VMID MICBIAS MICIN RLINEIN LLINEIN AVDD AGND HPVDD HPGND
1
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Type O I/O I I/O O I/O I I I/O I/O I O O O O O O O I I I P P P P
Function CODEC Clock Output CODEC Digital Audio Bit Clock CODEC Digital Audio Data (DAC) Input CODEC DAC Sample Rate Left/Right Clock CODEC ADC Digital Audio Data Output CODEC ADC Sample Rate Left/Right Clock CODEC Control Interface Selection CODEC Chip Select Interface Address Selection CODEC Data Input CODEC Data Clock CODEC Crystal Input/ Clock Input CODEC Crystal Output CODEC Left Channel Headphone Output (Analog Output) CODEC Right Channel Headphone Output (Analog Output) CODEC Left Channel Line Output (Analog Output) CODEC Right Channel Line Output (Analog Output) CODEC Mid-rail Reference Decoupling Point (Analog Output) CODEC Electret Microphone Bias (Analog Output) CODEC Microphone Input; (Analog Input, AC Coupled) CODEC Right Channel Line Input (Analog Input, AC Coupled) CODEC Left Channel Line Input (Analog Input, AC Coupled) CODEC Analog VDD CODEC Analog Ground CODEC Analog Headphone VDD CODEC Headphone Ground
Pull-Up/Down None Internal Pull-down1 None Internal Pull-down1 None Internal Pull-down1 Internal Pull-up1 Internal Pull-up1 None None None None None None None None None None None None None N/A N/A N/A N/A
To conserve power, the pull-up/pull-down is only present when the control register interface is active (= 0).
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June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
CODEC OPERATION
This section describes various operating modes for the CODEC.
Preliminary Technical Data
CODEC RESETTING
The CODEC contains a power-on reset circuit that resets the internal state of the device to a known condition. The power-on reset is applied as VDDEXT powers on and released only after the voltage level of VDDEXT crosses a minimum turn-off threshold. If VDDEXT later falls below a minimum turn-on threshold, the power-on reset is re-applied. The threshold voltages and associated hysteresis are shown in the Electrical Characteristics on Page 32. The programmer also has the ability to reset the device to a known state using the software control shown in Table 11. In SPI mode the software reset is applied on the rising edge of CSB and released on the next rising edge of CSCL. In TWI mode the reset is applied for the duration of the ACK signal (approximately one CSCL period) as shown in Figure 27 on Page 25. Table 11. Software Control of Reset
Register Bit Label Default Address Description
In applications where the CODEC is the system clock source, a suitable crystal is connected between the XTI/CODEC_MCLK input and XTO output pins as shown in Figure 18. For applications where the external system generates the reference clock, the external clock can be applied directly through the XTI/CODEC_MCLK input pin. No software configuration is necessary. In this situation, the oscillator circuit of the CODEC can be safely powered down to conserve power (see Power Down Modes on Page 25).
CODEC Clock
The CODEC can be clocked either by CODEC_MCLK or CODEC_MCLK divided by 2. This is controlled by software as shown in Table 12. Table 12. Software Control of CODEC Clock
Register Bit Label Address 000 1000 6 Default Description CODEC Clock Divider Select 1 = CODEC Clock is CODEC_MCLK / 2 0 = CODEC Clock is CODEC_MCLK
CLKIDIV2 0
000 1111 8:0 RESET Not Reset Reset Register 00000000 resets the CODEC
Minimizing Pop Noise At The Analog Outputs
Follow these procedures to minimize popping or click noises when the system is powered up or down. Power Up Sequence 1. Switch on power supplies. By default the CODEC is in standby mode, the DAC is digitally muted, and the audio interface and outputs are all off. 2. Set all required bits in the power down register 6 to `0'; except the OUTPD bit which should be set to `1' (default). 3. Set the required values in all other registers except for the ACTIVE bit in register 9. 4. Set the ACTIVE bit in register 9. 5. The last write of the sequence should set OUTPD to `0' (active) in register 6. This enables the DAC signal path, free of significant power-up noise. Power Down Sequence 1. Set the OUTPD bit to `1' (power down). 2. Remove the CODEC supplies.
Having a programmable CODEC_MCLK divider allows the device to be used in applications where higher frequency master clocks are available. For example the CODEC can support a master clock of 512 x fS while operating in a 256 x fS mode.
Crystal Oscillator
The CODEC includes a crystal oscillator circuit that allows the audio system reference clock to be generated on the CODEC. An external crystal is connected to the CODEC as shown in Figure 18. The crystal oscillator is a low radiation type designed for low EMI.
XTI/CODEC_MCLK XTO
CP
CP
GND
GND
Figure 18. Crystal Connection
CLOCKING
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronized. This clock is often referred to as the audio system master clock. The CODEC is capable of either generating this system clock or receiving it from an external source.
Rev. PrC |
The CODEC crystal oscillator provides an extremely low jitter clock. Low jitter clocks are a requirement for high quality audio ADC and DACs. The CODEC architecture is less susceptible than most converter techniques, but still requires clocks with less than approximately 1 ns of jitter. In applications where
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June 2008
Preliminary Technical Data
there is more than one master clock available, it is recommended that the clock be generated by the CODEC to maximize performance.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
* I2S * Frame Sync mode These are shown in Figure 19 on Page 17 to Figure 23 on Page 19. See Electrical Characteristics on Page 32 for timing information. These modes operate with 16-bit to 32-bit data except that 32-bit data is not supported in right justified mode. All four of these modes are MSB first. The digital audio interface takes the data from the internal ADC digital filter and places it on the ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls whether left or right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are synchronous with the CODEC_BCLK signal, with each data bit transition signified by a CODEC_BCLK highto-low transition. CODEC_BCLK can be an input or an output depending on whether the device is in master or slave mode. See Master and Slave Mode Operation on Page 21. The digital audio interface also receives the digital audio data for the internal DAC digital filters on the DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether left or right channel data is present on DACDAT. DACDAT and DACLRC are synchronous with the CODEC_BCLK signal with each data bit transition signified by a CODEC_BCLK highto-low transition. DACDAT is always an input. CODEC_BCLK and DACLRC are either outputs or inputs depending whether the CODEC is in master or slave mode. See Master and Slave Mode Operation on Page 21. In all modes DACLRC and ADCLRC must always change on the falling edge of CODEC_BCLK.
CODEC_CLKOUT
The CODEC clock is available to the external audio system on the CODEC_CLKOUT pin. The CODEC clock is buffered for driving external loads. There is no phase inversion between XTI/CODEC_MCLK, the CODEC clock and CODEC_CLKOUT but there will inevitably be some delay. The delay will be dependent on the load that CODEC_CLKOUT drives. See Electrical Characteristics on Page 32. CODEC_CLKOUT can also be divided by two. See Table 13 for the software control. CODEC_CLKOUT is disabled and set low whenever the device is in reset. Table 13. Programming CODEC_CLKOUT
Register Bit Label Address 000 1000 7 Default Description CODEC Clock Divider Select 1 = CODEC_CLKOUT is CODEC Clock / 2 0 = CODEC_CLKOUT is CODEC Clock
CLKODIV2 0
If CODEC_CLKOUT is not needed, the CODEC_CLKOUT buffer on the CODEC can be safely powered down to conserve power (see Power Down Modes on Page 25). If the programmer has a choice, fCODEC_CLKOUT = f CODEC_MCLK /2 is recommended to conserve power. CODEC_CLKOUT changes on the rising edge of CODEC_MCLK when f CODEC_MCLK /2 is selected.
DIGITAL AUDIO INTERFACES
The CODEC accommodates four digital audio interface formats. * Right justified * Left justified
1/fS
Left Justified Mode
Left justified mode is where the MSB is available on the first rising edge of CODEC_BCLK following a ADCLRC or DACLRC transition.
LEFT CHANNEL DACLRC/ ADCLRC
RIGHT CHANNEL
BCLK
DACDAT/ ADCDAT
1 MSB
2
3
n-2 n-1
n LSB
1 MSB
2
3
n-2 n-1
n LSB
Figure 19. Left Justified Mode
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June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
I2S Mode
I2S mode is where the MSB is available on the second rising edge of CODEC_BCLK following a DACLRC or ADCLRC transition.
1/fS
Preliminary Technical Data
LEFT CHANNEL DACLRC/ ADCLRC
RIGHT CHANNEL
CODEC_BCLK 1 CODEC_BCLK DACDAT/ ADCDAT 1 CODEC_BCLK
1 MSB
2
3
n-2 n-1
n LSB
1 MSB
2
3
n-2 n-1
n LSB
Figure 20. I2S Mode
Right Justified Mode
Right justified mode is where the LSB is available on the rising edge of CODEC_BCLK preceding a DACLRC or ADCLRC transition, yet MSB is still transmitted first.
1/fS
LEFT CHANNEL DACLRC/ ADCLRC
RIGHT CHANNEL
CODEC_BCLK
DACDAT/ ADCDAT
1 MSB
2
3
n-2 n-1
n LSB
1 MSB
2
3
n-2 n-1
n LSB
Figure 21. Right Justified Mode
Frame Sync/PCM Mode
In frame sync/PCM mode, the left channel MSB is available on either the first (mode B) or second (mode A) rising edge of CODEC_BCLK (selectable by LRP) following a rising edge of
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June 2008
Preliminary Technical Data
LRC. Right channel data immediately follows left channel data. Depending on word length, CODEC_BCLK frequency and sample rate--there may be unused CODEC_BCLK cycles between the LSB of the right channel data and the next sample.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
1/fS
LEFT CHANNEL DACLRC/ ADCLRC 1 CODEC_BCLK CODEC_BCLK
RIGHT CHANNEL
LEFT CHANNEL DACDAT/ ADCDAT 1 MSB INPUT WORD LENGTH (WL) 2 3 n-2 n-1 n LSB 1 2
RIGHT CHANNEL 3 n-2 n-1 n
Figure 22. Frame Sync/PCM Mode Audio Interface (Mode A, LRP=1)
1/fS
LEFT CHANNEL DACLRC/ ADCLRC 1 CODEC_BCLK CODEC_BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 MSB INPUT WORD LENGTH (WL) 2 3 n-2 n-1 n LSB 1 2 3 RIGHT CHANNEL
RIGHT CHANNEL
n-2 n-1
n
Figure 23. Frame Sync/PCM Mode Audio Interface (Mode B, LRP=0)
Operating the digital audio interface in frame sync mode makes support of the various sample rates and word lengths easier. The only requirement is that all data is transferred within the correct number of CODEC_BCLK cycles to suit the chosen word length.
Mark-Space Ratios
For the digital audio interface to offer similar support in the three other modes (Left Justified, I2S, and Right Justified), the DACLRC, ADCLRC and CODEC_BCLK frequencies, continuity and mark-space ratios need careful consideration. In slave mode the DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio. The CODEC_BCLK input need not be continuous. It is however required that there are sufficient CODEC_BCLK cycles for each DACLRC/ADCLRC transition to clock the chosen data word length. The non 50:50 requirement on the LRCs is useful in situ-
ations such as a USB 12 MHz clock. Simply dividing down a 12 MHz clock within the processor to generate LRCs and CODEC_BCLK will not generate the appropriate DACLRC or ADCLRC since they will no longer change on the falling edge of CODEC_BCLK. For example, with the 12 MHz/32kxfS mode there are 375 CODEC_MCLK per LRC. In these situations DACLRC/ADCLRC can be made non 50:50. In master mode, DACLRC and ADCLRC will be output with a 50:50 mark-space ratio with the CODEC_BCLK output at 64x base frequency (that is, 48 kHz). The exception again is in USB mode where CODEC_BCLK is always 12 MHz. For example in 12 MHz/32kxfS mode there are 375 master clocks per DACLRC period. Therefore DACLRC and ADCLRC outputs will have a mark space ratio of 187:188.
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June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Mode Configuration
The ADC and DAC digital audio interface modes are software configurable as indicated in Table 14. Dynamically changing the software format may result in erroneous operation of the interfaces and is therefore not recommended. Table 14. Digital Audio Interface Control
Register Bit Label Address Default Description
Preliminary Technical Data
0000111 1:0 FORMAT[1:0] 10
Audio Data Format Select 11 = Frame Sync Mode, Frame Sync Plus Two Data Packed Words 10 = I2S Format, MSB First, Left Justified 01 = MSB First, Left Justified 00 = MSB First, Right Justified Input Audio Data Bit Length Select 11 = 32-bits 10 = 24-bits 01 = 20-bits 00 = 16-bits DACLRC phase control (in left, right or I2S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low (opposite phasing in I2S mode) or Frame Sync mode A/B select (in Frame Sync mode only) 1 = MSB is available on second CODEC_BCLK rising edge after DACLRC rising edge 0 = MSB is available on first CODEC_BCLK rising edge after DACLRC rising edge DAC Left Right Clock Swap 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Bit Clock Invert 1 = Invert CODEC_BCLK 0 = Do Not Invert CODEC_BCLK
3:2 IWL[1:0]
10
4
LRP
0
5
LRSWAP
0
6
MS
0
7
BCLKINV
0
The length of the digital audio data is programmable at 16-, 20-, 24-, or 32-bits in the I2S or left justified modes only. The data is signed two's complement. Both ADC and DAC are fixed at the same data length. The ADC and DAC digital filters process data using 24-bits. If the ADC is programmed to output 16-bit or 20bit data then it strips the LSBs from the 24-bit data. If the ADC is programmed to output 32-bits then it packs the LSBs with zeros. If the DAC is programmed to receive 16-bit or 20-bit data, the CODEC packs the LSBs with zeros. If the DAC is programmed to receive 32-bit data, then it strips the LSBs. The DAC outputs can be swapped under software control using LRP and LRSWAP. Stereo samples are normally generated as a left/right sampled pair. LRSWAP reverses the order so that a left sample goes to the right DAC output and a right sample goes to the left DAC output. LRP swaps the phasing so that a right/left sampled pair is expected and preserves the correct channel phase difference.
To accommodate system timing requirements the interpretation of CODEC_BCLK may be inverted. This is especially appropriate for Frame Sync mode. ADCDAT lines are always outputs. They power up and return from standby low. DACDAT is always an input. It is expected to be set low by the audio interface controller when the CODEC is powered off or in standby. ADCLRC, DACLRC and CODEC_BCLK can be either outputs or inputs depending on whether the CODEC is configured as a master or slave. If the device is a master then the DACLRC and CODEC_BCLK signals are outputs that default low. If the device is a slave then the DACLRC and CODEC_BCLK are inputs. It is expected that these are set low by the audio interface controller when the CODEC is powered off or in standby. If right justified 32-bit mode is selected then the CODEC defaults to 24-bits.
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June 2008
Preliminary Technical Data
MASTER AND SLAVE MODE OPERATION
The CODEC can be configured as either a master or slave mode device. As a master mode device the CODEC controls sequencing of the data and clocks on the digital audio interface. As a slave device the CODEC responds with data to the clocks it receives over the digital audio interface. The mode is set with the MS bit of the control register as shown in Table 15. Table 15. Programming Master/Slave Modes
Register Bit Label Default Description Address 000 0111 6 MS 0 Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
AUDIO DATA SAMPLING RATES
The CODEC provides for two modes of operation (normal and USB) to generate the required DAC and ADC sampling rates. Use Table 16 to program normal and USB modes. Table 16. Sample Rate Control
Register Bit Label Address Default Description Mode Select 1 = USB mode (250/272 x fS) 0 = Normal mode (256/384 x fS) Base Over-Sampling Rate USB Mode 0 = 250 x fS 1 = 272 x fS Normal Mode 96/88.2 kHz 0 = 256 x fS 0 = 128 x fS 1 = 384 x fS 1 = 192 x fS 5:2 SR[3:0] 0000 ADC and DAC sample rate control (see Normal Mode Sample Rates and USB Mode Sample Rates on Page 23)
0001000 0 USB/ 0 NORMAL 1 BOSR 0
As a master mode device the CODEC controls the sequencing of data transfer (ADCDAT, DACDAT) and output of clocks (CODEC_BCLK, ADCLRC, DACLRC) over the digital audio interface. It uses the timing generated from either its on-board crystal or the CODEC_MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 24. ADCDAT is always an output from the CODEC and DACDAT is always an input to the CODEC whether in master or slave mode. As a slave device the CODEC sequences the data transfer (ADCDAT, DACDAT) over the digital audio interface in response to the external applied clocks (CODEC_BCLK, ADCLRC, DACLRC). This is illustrated in Figure 25. The CODEC relies on controlled phase relationships between audio interface CODEC_BCLK, DACLRC and the master CODEC_MCLK or CODEC_CLKOUT. To avoid timing hazards, see CODEC Clock Timing on Page 34 for detailed information.
CODEC_BCLK ADCLRC CODEC DACLRC ADCDAT DACDAT TSCLKx/RSCLKx TFSx BLACKFIN RFSx DRxPRI/DRxSEC DTxPRI/DTxSEC
In normal mode, the user controls the sample rate by using an appropriate CODEC_MCLK or crystal frequency and the sample rate control register setting. The CODEC can support sample rates from 8K samples/s up to 96K samples/s. In USB mode, a fixed CODEC_MCLK or crystal frequency of 12 MHz is used to generate sample rates from 8K samples/s to 96K samples/s. It is called USB mode since the common USB clock is 12 MHz. The CODEC can generate all the normal audio sample rates from this one master clock, without the need for different master clocks or PLL circuits. The CODEC offers the user the ability to sample the ADC and DAC at different rates under software control in both normal and USB modes. This reduces the burden on a controlling processor. However, signal processing in the ADC and DAC oversampling filters is tightly coupled to minimize power consumption. For that reason, only the combinations of sample rates listed in the following sections are supported. These rates are expected to be the combinations used in typical audio systems.
NOTE: ADC AND DAC CAN RUN AT DIFFERENT RATES
Figure 24. Master Mode
Normal Mode Sample Rates
CODEC_BCLK ADCLRC CODEC DACLRC ADCDAT DACDAT TSCLKx/RSCLKx TFSx BLACKFIN RFSx DRxPRI/DRxSEC DTxPRI/DTxSEC
In normal mode, the CODEC_MCLK/crystal oscillator is set up according to the desired sample rates of the ADC and DAC. For ADC or DAC sampling rates of 8, 32, 48 or 96 kHz, CODEC_MCLK frequencies of either 12.288 MHz (256 x fS) or 18.432 MHz (384 x fS) can be used. For ADC or DAC sampling rates of 8, 44.1 or 88.2 kHz--CODEC_MCLK frequencies of either 11.2896 MHz (256 x fS) or 16.9344 MHz (384 x fS) can be used. Table 17 can be used to set up the device for various sample rate combinations. For example if the user wishes to use the CODEC in normal mode with the ADC and DAC sample rates at 48 kHz
OTE: ADC AND DAC CAN RUN AT DIFFERENT RATES
Figure 25. Slave Mode
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June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
and 48 kHz respectively, then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 for a 12.288 MHz CODEC_MCLK; or with BOSR = 1, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 for a 18.432 MHz CODEC_MCLK. The ADC and DAC will operate with a digital filter of type 1. See Digital Filter Characteristics on Page 39 for an explanation of the different filter types. Table 17. Normal Mode Sample Rate Look-up
Sample Rate (kHz) CODEC_MCLK Sample Rate Register Setting1 Frequency (MHz) BOSR ADC DAC SR3 SR2 SR1 48 48 8 8 32 96 44.1 44.1 8.018 8.018 88.2 48 8 48 8 32 96 44.1 8.018 44.1 8.018 88.2 12.288 18.432 12.288 18.432 12.288 18.432 12.288 18.432 12.288 18.432 12.288 18.432 11.2896 16.9344 11.2896 16.9344 11.2896 16.9344 11.2896 16.9344 11.2896 16.9344
1
Preliminary Technical Data
The BOSR bit represents the base over-sampling rate. CODEC digital signal processing is carried out at this rate. In normal mode with BOSR = 0, the base over-sampling rate is 256 x fS. With BOSR = 1, the base over-sampling rate is 384 x fS. This can be used to determine the actual audio data rate produced by the ADC and required by the DAC.
Digital Filter Type SR0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 2 2
0 (256 x fS) 1 (384 x fS) 0 (256 x fS) 1 (384 x fS) 0 (256 x fS) 1 (384 x fS) 0 (256 x fS) 1 (384 x fS) 0 (256 x fS) 1 (384 x fS) 0 (128 x fS) 1 (192 x fS) 0 (256 x fS) 1 (384 x fS) 0 (256 x fS) 1 (384 x fS) 0 (256 x fS) 1 (384 x fS) 0 (256 x fS) 1 (384 x fS) 0 (128 x fS) 1 (192 x fS)
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1
Other combinations of BOSR and SR[3:0] are not valid
Examples 1. With ADC data rate 8 kHz, DAC data rate 48 kHz, and CODEC_MCLK = 12.288 MHz--program the device with BOSR = 0 (256 x fS), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0. The ADC output data rate will then be exactly 8 kHz (derived from (12.288 MHz/256) x1/6) and the DAC expects data at exactly 48 kHz (derived from 12.288 MHz/256). 2. With ADC data rate 8 kHz, DAC data rate 44.1 kHz, and CODEC_MCLK = 16.9344 MHz-- program the device with BOSR = 1 (384 x fS), SR3 = 1, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will output data at 8.018 kHz ((16.9344 MHz/384) x 2/11) instead of exactly 8.000 kHz. The DAC is still at exactly 44.1 kHz (derived from 16.9344 MHz/384).
A slight (sub 0.5%) pitch shift will occur in the 8 kHz audio data and (importantly) the user must ensure that the data across the digital interface is correctly synchronized at the 8.018 kHz rate.
Rev. PrC |
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June 2008
Preliminary Technical Data
The actual sample rates achieved are shown in Table 18. Table 18. Normal Mode Actual Sample Rates
Target Sampling Rate 8 kHz 32 kHz 44.1 kHz 48 kHz 88.2 kHz 96 kHz
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Actual Sampling Rate BOSR = 0 8 kHz (12.288 MHz/256) x 1/6 32 kHz (12.288 MHz/256) x 2/3 n/a 48 kHz 12.288 MHz/256 n/a 96 kHz (12.288 MHz/256) x 2 8.01 kHz (11.2896 MHz/256) x 2/11 n/a 44.1 kHz 11.2896 MHz/256 n/a 88.2 kHz (11.2896 MHz/256) x 2 n/a 8 kHz (18.432 MHz/384) x 1/6 32 kHz (18.432 MHz/384) x 2/3 n/a 48 kHz 18.432 MHz/384 n/a 96 kHz (18.432 MHz/384) x 2 BOSR = 1 8.018 kHz (16.9344 MHz/384) x 2/11 n/a 44.1 kHz 16.9344 MHz/384 n/a 88.2 kHz (16.9344 MHz/384) x 2 n/a CODEC_MCLK = 12.288 MHz CODEC_MCLK = 11.2896 MHz CODEC_MCLK = 18.432 MHz CODEC_MCLK = 16.9344 MHz
128/192 x fS Normal Mode
The normal mode sample rates are designed for standard 256 x fS and 384 x fS CODEC_MCLK rates. The CODEC can also be clocked from a 128 x fS or 192 x fS CODEC_MCLK for the limited sampling rates shown in Table 19. Table 19. 128 x fS Normal Mode Sample Rate Look-up
Sampling CODEC_MCLK Sample Rate Register Rate (kHz) Frequency Setting ADC DAC 48 48 6.144 MHz 9.216 MHz 44.1 44.1 5.6448 MHz 8.4672 MHz 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 Digital Filter BOSR SR3 SR2 SR1 SR0 Type 1 1 1 1 2 2 2 2
SR0 = 0. The ADC and DAC then operate with a digital filter of type 0. See Digital Filter Characteristics on Page 39 for an explanation of the different filter types. The BOSR bit represents the base over-sampling rate. This is the rate at which the CODEC digital signal processing is carried out. The sampling rate will always be a sub-multiple of the base oversampling rate. In USB mode, with BOSR = 0, the base over-sampling rate is 250 x fS. With BOSR = 1, the base over-sampling rate is 272 x fS. This can be used to determine the actual audio sampling rate produced by the ADC and required by the DAC. Examples 1. With ADC data sampling rate 8 kHz and DAC data sampling rate 48 kHz--program the device with BOSR = 0 (256 x fS), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will be exactly 8 kHz ((12 MHz/250) x 1/6) and the DAC expects data at exactly 48 kHz (12 MHz/250). 2. With ADC data rate 8 kHz and DAC data rate 44.1 kHz-- program the device with BOSR = 1 (272 x fS), SR3 = 1, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will output data at 8.021 kHz ((12 MHz/272) x 2/11) instead of exactly 8 kHz and the DAC will be 44.118 kHz (12 MHz/272). A slight (sub 0.5%) pitch shift occurs in the 8 kHz and 44.1 kHz audio data and (importantly) the user must ensure that the data across the digital interface is correctly synchronized at the 8.021 kHz and 44.117 kHz rates.
512/768xfS Normal Mode
512 x fS and 768 x fS CODEC_MCLK rates can be accommodated by using the CLKIDIV2 bit (register 8, bit 6). See Table 16 on Page 21 for software control. The CODEC clock will be divided by two so an external 512/768 x fS CODEC_MCLK will become 256/384 x fS internally. The CODEC otherwise operates as in Table 17 on Page 22 but with CODEC_MCLK at twice the specified rate.
USB Mode Sample Rates
In USB mode the CODEC_MCLK/crystal oscillator input is 12 MHz only. Table 20 can be used to set up the device to work with various sample rate combinations. For example if the ADC and DAC sample rates are 48 kHz and 48 kHz then the CODEC should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and
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ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
The actual sample rates achieved are shown in Table 21. Table 20. USB Mode Sample Rate Look-up
Sampling Rate CODEC_MCLK Sample Rate Register Digital (kHz) Frequency Setting1 Filter (MHz) ADC DAC BOSR SR3 SR2 SR1 SR0 Type 48 48 8 8.021 8 8.021 32 96 48 8.021 48 8 8.021 32 96 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 3 2 44.118 44.118 12.000 44.118 8.021
Preliminary Technical Data
Activating the Digital Audio Interface
To prevent communication problems, the audio interface is disabled (three-state with a 100 k pulldown) while the interface and sampling control are being programmed. Once programmed, the interface is activated by setting the ACTIVE bit shown in Table 22. Before changing the digital audio interface or sampling control register the ACTIVE bit should be reset then set. Table 22. Activating the Audio Interface
Register Address Bit Label 000 1001 0 Default Description Activate Interface 1 = Active 0 = Inactive
ACTIVE 0
44.118 12.000
SOFTWARE CONTROL INTERFACE
Software control can use either a 3-wire (SPI-compatible) or 2wire (TWI) interface. The interface is selected by setting the CMODE pin shown in Table 23. Table 23. Control Interface CMode Selection
CMODE 0 1 Interface format TWI SPI
88.235 88.235 12.000
1
Other combinations of BOSR and SR[3:0] are not valid
Table 21. USB Mode Actual Sample Rates
Target Actual Sampling Rate Sampling BOSR = 0 ( 250 x f ) BOSR = 1 (272 x f ) S S Rate 8 kHz 32 kHz 44.1 kHz 48 kHz 88.2 kHz 96 kHz 8 kHz 12 MHz/(250 x 48/8) 8.021 kHz 12 MHz/(272 x 11/2)
In SPI mode, CSDA is used for serial data and CSCL is used for the serial clock. In TWI mode, the state of the CSB pin allows the programmer to select one of two addresses.
32 kHz n/a 12 MHz/(250 x 48/32) n/a 48 kHz 12 MHz/250 n/a 96 kHz 12 MHz/125 44.117 kHz 12 MHz/272 n/a 88.235 kHz 12 MHz/136 n/a
SPI Mode
The CODEC can be controlled using an SPI serial interface. CSDA is used for the program data, CSCL is used to clock in the program data and CSB is used to latch the program data. The SPI interface protocol is shown in Figure 26.
CSB
CSCL
CONTROL ADDRESS
CONTROL DATA
CSDA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
NOTE: CSB IS EDGE SENSITIVE NOT LEVEL SENSITIVE. THE DATA IS LATCHED ON THE RISING EDGE OF CSB.
Figure 26. SPI Interface
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Preliminary Technical Data
TWI Mode
The CODEC can be controlled using a 2-wire TWI serial interface. CSDA is used for serial data and CSCL is used for the serial clock. The device operates as a slave device only. The CODEC
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
has one of two slave addresses that are selected by setting the state of pin 15, (CSB). The TWI interface protocol is shown in Figure 26.
CONTROL ADDRESS CSDA R ADDR R/W ACK DATA B15-8 ACK
CONTROL DATA DATA B7-0 ACK
CSCL
START
STOP
Figure 27. TWI Interface
To control the CODEC using the TWI bus, the master control device initiates a data transfer by establishing a start condition. This is defined by a high-to-low transition on CSDA while CSCL remains high, which indicates that an address and data transfer will follow. All peripherals on the TWI bus respond to the start condition and shift in the next eight bits (7-bit address plus read/write bit). The transfer is MSB first. The 7-bit address consists of a 6-bit base address plus a single programmable bit to select one of two available addresses for this device (see Table 24 on Page 25). If the correct address is received and the read/write bit is `0', indicating a write, the CODEC responds by pulling CSDA low on the next clock pulse (ACK). The CODEC is a write only device and will only respond when the read/write bit indicates a write. If the address is not recognized, the CODEC returns to the idle condition and waits for a new start condition and valid address. Table 24. TWI Address Selection
CSB State 0 1 Address 0011010 0011011
POWER DOWN MODES
The CODEC contains power conservation modes where various circuit blocks may be safely powered down. These modes are software programmable as shown in Table 25. Table 25. Power Conservation Mode Control
Register Bit Label Address 000 0110 0 LINEINPD Default Description 1 Line Input Power Down 1 = Enable Power Down 0 = Disable Power Down Microphone Input and Bias Power Down 1 = Enable Power Down 0 = Disable Power Down ADC Power Down 1 = Enable Power Down 0 = Disable Power Down DAC Power Down 1 = Enable Power Down 0 = Disable Power Down Line Output Power Down 1 = Enable Power Down 0 = Disable Power Down Oscillator Power Down 1 = Enable Power Down 0 = Disable Power Down CODEC_CLKOUT power down 1 = Enable Power Down 0 = Disable Power Down Power Off Device 1 = Device Power Off 0 = Device Power On
1
MICPD
1
2
ADCPD
1
3
DACPD
1
Once the CODEC has acknowledged a correct address, the controller sends eight data bits ([B15:B8]). The CODEC then acknowledges the data by pulling CSDA low for one clock pulse. The controller then sends the remaining eight data bits ([B7:B0]) and the CODEC then acknowledges again by pulling CSDA low. A stop condition is defined when there is a low-to-high transition on CSDA while CSCL is high. If a start or stop condition is detected out of sequence at any point in the data transfer then the device jumps to the idle state. After receiving a complete address and data sequence the CODEC returns to the idle state and waits for another start condition. Each write to a register requires the complete sequence of start condition, device address, and read/write bit followed by the 16-bit register address and data.
4
OUTPD
1
5
OSCPD
0
6
CLKOUTPD 0
7
POWEROFF 1
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ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
The power down control can be used to permanently disable functions when not required in certain applications. Or the modes can be used to dynamically power functions up and down depending on the operating mode, for example during playback or record. If dynamic implementations are used, the special instructions in the following sections should be followed.
Preliminary Technical Data
Standby Mode
The device can be put into a standby mode by powering down all the audio circuitry using the software control shown in Table 26. If the crystal oscillator and/or CODEC_CLKOUT pins are being used to derive the master clock, the crystal oscillator can be powered off without powering off CODEC_CLKOUT. Table 26. Standby Mode
POWER OFF CLKOUTPD LINEINPD 1 1 1 X LINEINPD X X Description
LINEINPD
Simultaneously powers down both line inputs. This can be done dynamically without audible effects either on the ADC or on the line outputs in bypass mode. This is useful when the device enters playback, pause or stop modes or when the microphone input is selected.
ADCPD 1 1
OUTPD
DACPD 1 1
OSCPD
MICPD
Simultaneously powers down both the microphone input and the microphone bias. If this is done dynamically audible pops through the ADC will result, but they will only be audible if the microphone input is selected to the ADC at the time. If the state of MICPD is changed, the controlling processor should switch the line inputs to the ADC (INSEL) before changing MICPD. This is useful when the device enters playback, pause or stop modes or when the microphone input is not selected.
0 0
0 1
0 0
1 1
1 1
MICPD 1 X MICPD X X
STANDBY, with Crystal Oscillator and CODEC_CLKOUT available STANDBY, with Crystal Oscillator available, CODEC_CLKOUT not available STANDBY, Crystal Oscillator and CODEC_CLKOUT not available.
0
1
1
1
1
1
ADCPD
Powers down the ADC and ADC filters. If this is done dynamically audible pops will result if any signals were passing through the ADC. To avoid popping when the ADC is to be powered down, either mute the microphone input (MUTEIN) or mute the MUTELINEIN, then change ADCPD. This is useful when the device enters playback, pause or stop modes regardless whether microphone or line inputs are selected.
In standby mode the control interface, and a small portion of the digital and areas of the analog circuitry remain active. The active analog includes the analog VMID reference so that the analog line inputs, line outputs and headphone outputs remain biased to VMID. This reduces audible effects from dc glitches when entering or leaving standby mode.
Power Off Mode
The device can be powered off by writing to the POWEROFF bit of the power down register. In the power off mode, the control interface and a small portion of the digital circuits remain active. The analog VMID reference is disabled. As in standby mode, the crystal oscillator and/or CODEC_CLKOUT pin can be independently controlled. See Table 27. Table 27. Poweroff Mode
POWER OFF CLKOUTPD Description
DACPD
Powers down the DAC and DAC digital filters. If this is done dynamically audible pops will result. To prevent pop--the DAC should first be soft-muted (DACMU), then the output should be de-selected from the line and headphone output (DACSEL), and then the DAC powered down (DACPD). This is useful when the device enters record, pause, stop or bypass modes.
OUTPD
Powers down the line and headphone outputs. If this is done dynamically audible pops may result unless the DAC is first soft-muted (DACMU). This is useful when the device enters record, pause or stop modes.
1
0
0
X
X
X
ADCPD
OUTPD
DACPD
OSCPD
POWEROFF, with Crystal Oscillator and CODEC_CLKOUT available POWEROFF, with Crystal Oscillator available, CODEC_CLKOUT not available POWEROFF, Crystal Oscillator and CODEC_CLKOUT not available
1
1
0
X
X
X
OSCPD
Powers off the on board crystal oscillator. The CODEC_MCLK input functions independently of the oscillator being powered down.
1 1 1 X X X
CLKOUTPD
Powers down the CODEC_CLKOUT pin. This conserves power and reduces digital noise and RF emissions. CODEC_CLKOUT is tied low when powered down.
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June 2008
Preliminary Technical Data REGISTER MAP
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
16-bits per register (7-bit address plus nine bits of data). These can be controlled using either the two wire USB or three wire SPI interface.
The complete register map is shown in Table 28. The detailed description can be found in Table 29 on Page 27 and in the relevant text of the device description. There are 11 registers with Table 28. Program Register Mapping
Register B15 B14 B13 B12 B11 B10 B9 Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 B8 B7
B6
B5 Data
B4
B3
B2
B1
B0
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R15
LRINBOTH LINMUTE 0 0 LINVOL RLINBOTH RINMUTE 0 0 RINVOL LRHPBOTH LZCEN LHPVOL RLHPBOTH RZCEN RHPVOL 0 SIDEATT SIDETONE DACSEL BYPASS INSEL MUTEMIC MICBOOST 0 0 0 0 HPOR DACMU DEEMPH ADC HPD 0 PWROFF CLKOUTPD OSCPD OUTPD DACPD ADCPD MICPD LINEINPD 0 CODEC_BCLKINV MS LRSWAP LRP IWL FORMAT 0 CLKODIV2 CLKIDIV2 SR BOSR USB/NORM 0 0 0 0 0 0 0 0 ACTIVE RESET
Table 29. Register Descriptions
Register Address Register 0 000 0000 Left Line In Bit Label Default Description 4:0 LINVOL[4:0] 10111 Left Channel Line Input Volume Control ( 0 dB ) 11111 = +12 dB in 1.5 dB steps down to 00000 = -34.5 dB 7 LINMUTE 1 Left Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute 8 LRINBOTH 0 Left to Right Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of LINVOL[4:0] and LINMUTE to RINVOL[4:0] and RINMUTE 0 = Disable Simultaneous Load Register 1 4:0 RINVOL[4:0] 10111 Right Channel Line Input Volume Control 000 0001 ( 0 dB ) 11111 = +12 dB in 1.5 dB Steps Down to 00000 = -34.5 dB Right Line In 7 RINMUTE 1 Right Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute 8 RLINBOTH 0 Right to Left Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of RINVOL[4:0] and RINMUTE to LINVOL[4:0] and LINMUTE 0 = Disable Simultaneous Load 6:0 LHPVOL 1111001 Left Channel Headphone Output Volume Control Register 2 000 0010 [6:0] ( 0 dB ) 1111111 = +6 dB in 1 dB Steps Down to 0110000 = -73 dB Left Headphone Out 0000000 to 0101111 = MUTE 7 LZCEN 0 Left Channel Zero Cross Detect Enable 1 = Enable 0 = Disable 8 LRHPBOTH 0 Left to Right Channel Headphone Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of LHPVOL[6:0] and LZCEN to RHPVOL[6:0] and RZCEN 0 = Disable Simultaneous Load
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ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Table 29. Register Descriptions (Continued)
Register Address Bit Label Register 3 6:0 RHPVOL 000 0011 [6:0] Right Headphone Out
Preliminary Technical Data
Register 4 000 0100 Analog Audio Path Control
Register 5 000 0101 Digital Audio Path Control
Default Description 1111001 Right Channel Headphone Output Volume Control ( 0 dB ) 1111111 = +6 dB in 1 dB Steps Down to 0110000 = -73 dB 0000000 to 0101111 = MUTE 7 RZCEN 0 Right Channel Zero Cross Detect Enable 1 = Enable 0 = Disable 8 RLHPBOTH 0 Right to Left Channel Headphone Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of RHPVOL[6:0] and RZCEN to LHPVOL[6:0] and LZCEN 0 = Disable Simultaneous Load 0 MICBOOST 0 Microphone Input Level Boost 1 = Enable Boost 0 = Disable Boost 1 MUTEMIC 1 Mic Input Mute to ADC 1 = Enable Mute 0 = Disable Mute 2 INSEL 0 Microphone/Line Input Select to ADC 1 = Microphone Input Select to ADC 0 = Line Input Select to ADC 3 BYPASS 1 Bypass Switch 1 = Enable Bypass 0 = Disable Bypass 4 DACSEL 0 DAC Select 1 = Select DAC 0 = Do Not Select DAC 5 SIDETONE 0 Side Tone Switch 1 = Enable Side Tone 0 = Disable Side Tone 7:6 SIDEATT[1:0] 00 Side Tone Attenuation 11 = -15 dB 10 = -12 dB 01 = -9 dB 00 = -6 dB 0 ADCHPD 0 ADC High Pass Filter Enable 1 = Disable High Pass Filter 0 = Enable High Pass Filter 2:1 DEEMP[1:0] 00 De-emphasis Control 11 = 48 kHz 10 = 44.1 kHz 01 = 32 kHz 00 = Disable 3 DACMU 1 DAC Soft Mute Control 1 = Enable Soft Mute 0 = Disable Soft Mute 4 HPOR 0 Store DC Offset When High Pass Filter Disabled 1 = Store Offset 0 = Clear Offset
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June 2008
Preliminary Technical Data
Table 29. Register Descriptions (Continued)
Register Address Register 6 000 0110 Power Down Control Bit Label 0 LINEINPD
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Register 7 000 0111 Digital Audio Interface Format
Default Description 1 Line Input Power Down 1 = Enable Power Down 0 = Disable Power Down 1 MICPD 1 Microphone Input and Bias Power Down 1 = Enable Power Down 0 = Disable Power Down 2 ADCPD 1 ADC Power Down 1 = Enable Power Down 0 = Disable Power Down 3 DACPD 1 DAC Power Down 1 = Enable Power Down 0 = Disable Power Down 4 OUTPD 1 Outputs Power Down 1 = Enable Power Down 0 = Disable Power Down 5 OSCPD 0 Oscillator Power Down 1 = Enable Power Down 0 = Disable Power Down 6 CLKOUTPD 0 CODEC_CLKOUT Power down 1 = Enable Power Down 0 = Disable Power Down 7 POWEROFF 1 POWEROFF mode 1 = Enable POWEROFF 0 = Disable POWEROFF 1:0 FORMAT[1:0] 10 Audio Data Format Select 11 = Frame Sync Mode, Frame Sync Plus Two Data Packed Words 10 = I2S Format, MSB-First Left-1 Justified 01 = MSB-First, Left Justified 00 = MSB-First, Right Justified 3:2 IWL[1:0] 10 Input Audio Data Bit Length Select 11 = 32-bits 10 = 24-bits 01 = 20-bits 00 = 16-bits 4 LRP 0 DACLRC Phase Control (in Left, Right or I2S Modes) 1 = Right Channel DAC Data When DACLRC High 0 = Right Channel DAC Data When DACLRC Low (Opposite Phasing in I2S Mode) or Frame Sync Mode A/B Select (in Frame Sync Mode Only) 1 = MSB is Available on Second CODEC_BCLK Rising Edge After DACLRC Rising Edge 0 = MSB is Available on First CODEC_BCLK Rising Edge After DACLRC Rising Edge 5 LRSWAP 0 DAC Left Right Clock Swap 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right 6 MS 0 Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode 7 BCLKINV 0 Bit Clock Invert 1 = Invert CODEC_BCLK 0 = Do Not Invert CODEC_BCLK
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ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Table 29. Register Descriptions (Continued)
Register Address Register 8 000 1000 Sampling Control Bit Label 0 USB/ NORMAL 1 BOSR
Preliminary Technical Data
5:2 SR[3:0] 6 CLKIDIV2
7
CLKODIV2
Register 9 000 1001 Active Control Register 10 000 1111 Reset Register
0
ACTIVE
8:0 RESET
Default Description 0 Mode Select 1 = USB Mode (250/272 x fS) 0 = Normal Mode (256/384 x fS) 0 Base Over-Sampling Rate USB Mode 0 = 250 x fS 1 = 272 x fS Normal Mode 0 = 256 x fS 1 = 384 x fS 0000 ADC and DAC Sample Rate Control; See USB Mode and Normal Mode Sample Rate Sections for Operation 0 CODEC Clock Divider Select 1 = CODEC Clock is CODEC_MCLK Divided by Two 0 = CODEC Clock is CODEC_MCLK 0 CODEC_CLKOUT Divider Select 1 = CODEC_CLKOUT is CODEC Clock Divided by Two 0 = CODEC_CLKOUT is CODEC Clock 0 Activate Interface 1 = Active 0 = Inactive not reset Reset Register Writing 0000 0000 to Register Resets Device
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June 2008
Preliminary Technical Data SPECIFICATIONS
Component specifications are subject to change without notice.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
OPERATING CONDITIONS
Parameter AVDD HPVDD VILC VIHC VOLC VOHC
1
Conditions Analog VDD Headphone VDD (Analog) CODEC Low Level Input Voltage
1
Min 1.8 1.8 0.7 x VDDEXT
Typical Max 3.6 3.6
Unit V V V
0.3 x VDDEXT V
1 1
CODEC High Level Input Voltage1 CODEC Low Level Output Voltage CODEC Low Level Output Voltage
0.1 x VDDEXT V 0.9 x VDDEXT V
Parameter value applies to digital signal pins (ADCDAT, ADCLRC, CODEC_BCLK, CSB, CODEC_CLKOUT, CMODE, DACDAT, DACLRC, CSCL, CSDA, XTI/CODEC_MCLK, XTO).
POWER CONSUMPTION
Table 30. Powerdown Mode Current Consumption
POWEROFF CLKOUTPD LINEINPD Current Consumption1, 2, 3, 4, 5 Typical AVDD (1.8V) HPVDD (1.8V) 0.6 0.6 VDDEXT (1.8V) 0.9 0.9 0.9 0.9 0.6 0.6 Unit
OUTPD
ADCPD 0 1 0 0 1 1 1 1
DACPD
OSCPD
Mode Description Record and Playback All active, Oscillator Enabled Playback Only Oscillator Enabled Record Only Line Record, Oscillator Enabled Mic Record, Oscillator Enabled Side Tone (Microphone Input to Headphone Output) Clock Stopped Analog Bypass (Line-in to Line-out) Clock Stopped Standby Clock Stopped Power Down Clock Stopped
1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 0 1 1 1 1 1 1
0 1 1 0 0 1 1 1
MICPD
0 1 0 1 1 0 1 1
6 1.7 3.9 3.6 0.8 1.1 8 0.2
mA mA mA mA mA mA A
0.2
0.2
A
These current consumption values are for the CODEC alone. Please refer to the published ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSPBF527 Revision PrD datasheet for the additional current consumption of the Blackfin processor. 2 AVDD, HPVDD, VDDEXT = 1.8V, AGND = 0V, TA = +25C. Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 x fS (12.288 MHz). 3 All values are quiescent, with no signal. 4 All values are measured with the audio interface in master mode (MS = 1). 5 The power dissipation in the headphone itself is not included in this table.
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June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
ELECTRICAL CHARACTERISTICS
Parameter1 Line Input to ADC SNR SNR DR THD SNR DR THD SNR SNR DR THD THD SNR THD THD PO PO SNR THD THD SNR
1
Preliminary Technical Data
Min Typical Max Unit tbd 85 85 tbd 88 -76 80 70 -55 tbd 95 93 tbd 90 -80 -90 tbd 90 -83 -92 9 18 tbd 95 -62 tbd tbd tbd 90 tbd tbd tbd dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB mW mW dB dB dB dB
Conditions2 Signal to Noise Ratio Signal to Noise Ratio Dynamic Range A-weighted, 0 dB Gain @ fS = 48 kHz A-weighted, 0 dB Gain @ fS = 96 kHz A-weighted, -60 dB Full Scale Input 0 dB Gain, fS = 48 kHz, 40 k Source Impedance A-weighted, 0 dB Gain A-weighted, -60 dB Full Scale Input Load = 10 k, 50 pF A-weighted, 0 dB Gain @ fS = 48 kHz A-weighted, 0 dB Gain @ fS = 96 kHz A-weighted, -60 dB Full Scale Input
Total Harmonic Distortion -1 dB Input, 0 dB Gain Signal to Noise Ratio Dynamic Range
Microphone Input to ADC
Total Harmonic Distortion 0 dB Input, 0 dB Gain Signal to Noise Ratio Signal to Noise Ratio Dynamic Range
Line Output for DAC Playback Only
Total Harmonic Distortion 1 kHz, 0 dB Total Harmonic Distortion 1 kHz, -3 dB Load = 10 k , 50 pF, No Gain on Input, Bypass Mode Signal to Noise Ratio Total Harmonic Distortion 1 kHz, 0 dB Total Harmonic Distortion 1 kHz, -3 dB Maximum Output Power Maximum Output Power Signal to Noise Ratio RL = 32 RL = 16 A-weighted
Analog Line Input to Line Output
Stereo Headphone Output
Total Harmonic Distortion 1 kHz, -5 dB, RL = 32 , Full Scale Input Total Harmonic Distortion 1 kHz,-2 dB, RL = 32 , Full Scale Input Signal to Noise Ratio
Microphone Input to Headphone Output Side Tone Mode
SNR is the ratio of output level with 1 kHz full scale input, to the output level with the input short-circuited, measured `A' weighted over a 20Hz to 20 kHz bandwidth using an audio analyzer. Ratio of output level with 1 kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted over a 20 Hz to 20 kHz bandwidth. All performance measurements are done with a 20 kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in these specifications. The low pass filter removes out of band noise; which is not audible but may affect dynamic specification values. VMID is decoupled with 10 F and 0.1 F capacitors (smaller values may result in reduced performance). 2 AVDD, HPVDD, VDDEXT = 1.8V, AGND = 0V, TA = +25C. Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 x fS (12.288 MHz) unless otherwise stated.
Signal-to-noise ratio (SNR) (dB) is a measure of the difference in level between the full scale output and the output with no signal applied. Dynamic range (DR) (dB) is a measure of the difference between the highest and lowest portions of a signal, normally a THD+N measurement at 60 dB below full scale. The measured signal is then corrected by adding the 60 dB to it. For example THD+N @ -60 dB = -32 dB, DR = 92 dB. Total Harmonic Distortion Plus Noise (THD+N) (dB) is a ratio of the rms values of (Noise + Distortion)/Signal.
Channel Separation (dB)--Also known as crosstalk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.
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June 2008
Preliminary Technical Data
PACKAGE INFORMATION
The information presented in Figure 28 and Table 31 provides details about the package branding for the ADSPBF523C/ADSP-BF525C/ADSP-BF527C processor. For a complete listing of product availability, see Ordering Guide on Page 44.
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
a
ADSP-BF527KBCZ6C1X tppZccc vvvvvv.x n.n yyww country_of_origin
B
Figure 28. Product Information on Package
Table 31. Package Brand Information
Brand Key t pp Z ccc vvvvvv.x n.n yyww Field Description Temperature Range Package Type Lead Free Option See Ordering Guide Assembly Lot Code Silicon Revision Date Code
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June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
CODEC CLOCK TIMING
Preliminary Technical Data
tXTIL
XTI/CODEC_MCLK tXTIH t XTIY
Figure 29. CODEC Clock Timing Requirements
Table 32. CODEC Clock Timing Requirements
Parameter tXTIH XTI/CODEC_MCLK System clock pulse width high tXTIL XTI/CODEC_MCLK System clock pulse width low tXTIY XTI/CODEC_MCLK System clock cycle time XTI/CODEC_MCLK Duty cycle
1
Test Conditions1
Min 18 18 54 40:60
Typical Max Unit ns ns ns 60:40
AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25C, Slave Mode fs = 48 kHz, XTI/CODEC_MCLK = 256 x fs unless otherwise stated.
XTI/CODEC_MCLK tCOP
CODEC_CLKOUT
CODEC_CLKOUT / 2
Figure 30. CODEC_CLKOUT Timing Requirements
Table 33. Clock Out Timing Requirements
Parameter tCOP CODEC_CLKOUT propagation delay from XTI/CODEC_MCLK falling edge
1
Test Conditions1
Min Typical Max Unit 0 10 ns
AVDD, HPVDD, VDDEXT = 3.3V, AGND = 0V, TA = +25C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 x fS unless otherwise stated.
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June 2008
Preliminary Technical Data
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
DIGITAL AUDIO INTERFACE--MASTER MODE
CODEC_BCLK (Output)
tDL ADCLRC DAC/LRC (Outputs)
tDDA ADCDAT
DACDAT
tDST
tDHT
Figure 31. Digital Audio Data Timing--Master Mode
Table 34. Digital Audio Data Timing--Master Mode
Parameter tDL ADCLRC/DACLRC propagation delay from CODEC_BCLK falling edge Test Conditions1 Min Typical Max Unit 0 0 10 10 10 15 ns ns ns ns
tDDA ADCDAT propagation delay from CODEC_BCLK falling edge tDST DACDAT setup time to CODEC_BCLK rising edge tDHT DACDAT hold time from CODEC_BCLK rising edge
1
AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 x fS unless otherwise stated.
Rev. PrC |
Page 35 of 44 |
June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
DIGITAL AUDIO INTERFACE--SLAVE MODE
tBCH tBCL
Preliminary Technical Data
CODEC_BCLK tBCY
DACLRC/ ADCLRC t DS tLRH tLRSU
DACDAT tDD ADCDAT t DH
Figure 32. Digital Audio Data Timing--Slave Mode
Table 35. Digital Audio Data Timing--Slave Mode
Parameter tBCY CODEC_BCLK cycle time tBCH CODEC_BCLK pulse width high tBCL CODEC_BCLK pulse width low tLRSU DACLRC/ADCLRC set-up time to CODEC_BCLK rising edge tLRH DACLRC/ADCLRC hold time from CODEC_BCLK rising edge tDS tDH tDD
1
Test Conditions1
Min Typical Max Unit 50 20 20 10 10 10 10 0 10 ns ns ns ns ns ns ns ns
DACDAT set-up time to CODEC_BCLK rising edge DACDAT hold time from CODEC_BCLK rising edge ADCDAT propagation delay from CODEC_BCLK falling edge
AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 x fS unless otherwise stated.
Rev. PrC |
Page 36 of 44 |
June 2008
Preliminary Technical Data BLACKFIN SPI/TWI INTERFACE TIMING
tCSL
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
tCSH
CSB
tSCY tSCH tSCL tSCS
tCSS
CSCL
CSDA
LSB t t
DSU
DHO
Figure 33. Program Register Input Timing--SPI Serial Control Mode
Table 36. Program Register Input Timing--SPI Serial Control Mode
Parameter tSCS CSCL rising edge to CSB rising edge tSCY CSCL pulse cycle time tSCL CSCL pulse width low tSCH CSCL pulse width high tDSU CSDA to CSCL set-up time tDHO CSCL to CSDA hold time tCSL CSB pulse width low tCSH CSB pulse width high tCSS CSB rising to CSCL rising
1 o
Test Conditions1
Min Typical Max Unit 60 80 20 20 20 20 20 20 20 ns ns ns ns ns ns ns ns ns
AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25 C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 x fS unless otherwise stated.
Rev. PrC |
Page 37 of 44 |
June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
t3 CSDA t6 CSCL t1 t10 t t t5 t3
Preliminary Technical Data
2
4
t
8
t7
Figure 34. Program Register Input Timing--TWI Serial Control Mode
Table 37. Program Register Input Timing--TWI Serial Control Mode
Parameter CSCL Frequency t1 t2 t3 t4 t5 t6 t7 t8 CSCL Low Pulsewidth CSCL High Pulsewidth Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time CSDA, CSCL Rise Time CSDA, CSCL Fall Time Setup Time (Stop Condition) 600 Test Conditions1 Min Typical Max Unit 0 1.3 600 600 600 100 526 kHz us ns ns ns ns 300 ns 300 ns ns 900 ns
o
t10 Data Hold Time
1
AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25 C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 x fS unless otherwise stated.
Rev. PrC |
Page 38 of 44 |
June 2008
Preliminary Technical Data DIGITAL FILTER CHARACTERISTICS
Stop Band Attenuation (dB) is the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple is any variation of the frequency response in the pass-band region Table 38. Digital Filter Characteristics
Parameter ADC Filter Passband Passband Passband Ripple Stopband Stopband Attenuation f > 0.5465 x fS High Pass Filter Corner Frequency -3 dB High Pass Filter Corner Frequency -0.5 dB High Pass Filter Corner Frequency -0.1 dB DAC Filter Passband Passband Passband Ripple Stopband Stopband Attenuation f > 0.5465 x fS 0.03 dB -6 dB 0.05 dB -6 dB Conditions
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
The ADC and DAC employ different digital filters. There are four types of digital filter, called Type 0, 1, 2 and 3. The performance of Types 0 and 1 is listed in Table 38, the responses of all filters is shown in the proceeding pages.
Min tbd x fS
Typical Max tbd x fS 0.5 x fS tbd
Unit
dB dB
tbd x fS tbd 3.7 10.4 21.6 tbd x fS 0.5 x fS tbd tbd x fS tbd dB dB tbd x fS Hz Hz Hz
Table 39. ADC/DAC Digital Filters Group Delay
Group Delay Mode 0 1 2 3 DAC Filters 11/ fS 18 / fS 5 / fS 5 / fS ADC Filters 12 / fS 20 / fS 3 / fS 6 / fS
ADC HIGH PASS FILTER
The CODEC has a selectable digital high pass filter to remove dc offsets. The filter response is characterized by the following polynomial. H ( z ) = ( 1 - z -1 ) ( 1 - 0.9995 x z -1 )
Rev. PrC |
Page 39 of 44 |
June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
289-BALL MINI-BGA PINOUT
Table 40 lists the mini-BGA pinout by signal mnemonic. Table 41 on Page 42 lists the mini-BGA pinout by ball number. Table 40. 289-Ball Mini-BGA Ball Assignment (Alphabetically by Signal)
Signal ABE0/SDQM0 ABE1/SDQM1 ADCDAT ADCLRC ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 HPGND AGND AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE HPVDD AVDD AWE CODEC_BCLK BMODE0 Ball No. AB9 AC9 A16 A15 AB8 AC8 AB7 AC7 AC6 AB6 AB4 AB5 AC5 AC4 AB3 AC3 AB2 AC2 AA2 W2 Y2 AA1 AB1 G17 H22 Signal CSB CSCL CSDA DACDAT DACLRC DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 EMU GND GND Ball No. D23 B23 C23 A18 A17 Y1 V2 W1 U2 V1 U1 T2 T1 R1 P1 P2 R2 N1 N2 M2 M1 J2 A1 A23 B6 J9 J10 J11 J12 J13 J14 J15 K9 K10 K11 K12 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. L14 L15 M9 Signal PF5 PF6 PF7 Ball Signal No. B10 RESET B12 RHPOUT B13 RLINEIN B16 ROUT A20 RTXI B15 RTXO B17 SA10 B18 SCAS B19 SCKE A9 H2 G1 H1 F1 D1 D2 C2 B1 C1 B2 B4 B3 A2 A3 A4 A5 SCL SMS SRAS SS/PG SWE TCK TDI TDO TMS TRST USB_DM USB_DP USB_ID A10 SDA
Preliminary Technical Data
Ball No. V22 B21 F23 G22 U23 V23
Signal VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT
Ball Signal No. R17 VDDMEM T17 VDDMEM U17 VDDMEM B5 H8 H9 VDDMEM VDDMEM VDDMEM
Ball No. U8 U9 U10 U11 U12 U13 U14 U15 U16 AC12 W23 W22 Y23 G23 AC18 AB22 P23 A21
M10 PF8 M11 PF9 M12 PF10 M13 PF11 M14 PF12 M15 PF13 N9 N10 N11 N12 N13 N14 N15 P9 P10 P11 P12 P13 P14 P15 R9 R10 R11 R12 R13 R14 R15 T22 AC1 PF14 PF15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 PH1 PH2 PH3 PH4 PH6 PH7 PH8 PH9
AC10 VDDINT AC11 VDDINT AB13 VDDINT B22 C22 VDDINT VDDINT
H10 VDDMEM H11 VDDMEM H12 VDDMEM H13 VDDOTP H14 VDDRTC H15 VDDUSB H16 VDDUSB J8 J16 K8 L8 M8 M16 N8 N16 P8 P16 R8 R16 T8 T9 T10 T11 T12 T13 T14 T15 T16 VMID VROUT VRSEL
AC13 VDDINT AB12 VDDINT AC20 VDDINT AB10 VDDINT L1 J1 K1 L2 K2 VDDINT VDDINT VDDINT VDDINT VDDINT
K16 XTAL L16 XTO
XTI/CODEC_MCLK A22
AB21 VDDINT AA22 VDDINT Y22 VDDINT
EXT_WAKE AC19 GND
USB_RSET AC21 VDDINT USB_VBUS AB20 VDDINT USB_VREF AC22 VDDINT USB_XI AB23 VDDINT AA23 VDDINT G7 G8 G9 G10 G11 G12 G13 G14 G15 VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT
AC17 GND AB16 GND AC16 GND AB15 GND AC15 GND AC14 GND AB17 GND G16 J22 A19 G2 GND GND GND GND
A11 USB_XO A12 VDDEXT A13 VDDEXT B14 VDDEXT A14 VDDEXT K23 VDDEXT K22 VDDEXT L23 VDDEXT L22 VDDEXT T23 VDDEXT
AC23 PH5
LHPOUT B20 LLINEIN E23 LOUT F22 MICBIAS H23
AB14 GND
VDDMEM J7
Rev. PrC |
Page 40 of 44 |
June 2008
Preliminary Technical Data
Signal BMODE1 BMODE2 BMODE3 CLKBUF CLKIN CLKOUT CMODE Ball No. F2 E1 E2 Signal GND GND GND GND GND GND Ball No. K13 K14 K15 L9 L10 L11 L12 L13 Signal MICIN NMI PF0 PF1 PF2 PF3 PF4 Ball No. J23 U22 A7 B8 A8 B9 B11
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Signal PH10 PH11 PH13 PH14 PH15 PPIFS1/TMR0 Ball Signal No. M22 VDDEXT R22 VDDEXT M23 VDDEXT N22 VDDEXT N23 VDDEXT P22 VDDEXT VDDEXT VDDEXT B7 Ball No. H7 H17 J17 K17 L17 N17 P17 Signal Ball Signal No. Ball No.
Table 40. 289-Ball Mini-BGA Ball Assignment (Alphabetically by Signal) (Continued) (Continued)
VDDMEM K7 VDDMEM L7 VDDMEM M7 VDDMEM N7 VDDMEM P7 VDDMEM T7 VDDMEM U7
VPPOTP AB11 PH12
CODEC_CLKOUT D22 R23 E22
AB19 GND AB18 GND
M17 VDDMEM R7
PPICLK/TMRCLK A6
Rev. PrC |
Page 41 of 44 |
June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Table 41. 289-Ball Mini-BGA Ball Assignment (Numerically by Ball Number)
Ball Signal No. A1 A2 A3 A4 A5 A6 A7 A8 A9 GND PG12 PG13 PG14 PG15 PPICLK/TMRCLK PF0 PF2 PF14 Ball Signal No. B23 CSCL C1 C2 PG8 PG6 Ball Signal No. H22 AGND H23 MICBIAS J1 J2 J7 J8 J9 J11 J12 J13 J14 J15 J16 J17 J22 J23 K1 K2 K7 K8 K9 TDI EMU VDDINT GND GND GND GND GND GND GND VDDINT VDDEXT AVDD MICIN TDO TRST VDDINT GND Ball Signal No. L22 PH8 L23 PH7 M1 M2 M8 M9 DATA15 DATA14 VDDINT GND
Preliminary Technical Data
Ball Signal No. P22 PH15 P23 XTAL R1 R2 R8 R9 DATA8 DATA11 VDDINT GND Ball No. U22 U23 V1 V2 V23 W1 W2 Signal NMI RTXI DATA4 DATA1 RESET RTXO DATA2 ADDR16 Ball No. AC5 AC6 AC7 AC8 AC9 Signal ADDR9 ADDR5 ADDR4 ADDR2 ABE1/SDQM1
C22 SDA C23 CSDA D1 D2 PG4 PG5
VDDMEM M7
VDDMEM R7
VDDMEM V22
AC10 SA10 AC11 SCAS AC12 VDDOTP AC13 SMS AC14 ARDY AC15 AOE AC16 AMS2 AC17 AMS0 AC18 VROUT AC19 EXT_WAKE AC20 SS/PG AC21 USB_RSET AC22 USB_VREF AC23 GND
D22 CODEC_CLKOUT J10 D23 CSB E1 E2 BMODE2 BMODE3
M10 GND M11 GND M12 GND M13 GND M14 GND M15 GND M16 VDDINT M17 VDDEXT M22 PH10 M23 PH12 N1 N2 N8 N9 DATA12 DATA13 VDDINT GND
R10 GND R11 GND R12 GND R13 GND R14 GND R15 GND R16 VDDINT R17 VDDEXT R22 PH11 R23 CLKIN T1 T2 T8 T9 DATA7 DATA6 VDDINT VDDINT
W22 VDDUSB W23 VDDRTC Y1 Y2 Y22 Y23 AA1 AA2 DATA0 ADDR17 USB_ID VDDUSB ADDR18 ADDR15
A10 PF15 A11 PH0 A12 PH1 A13 PH2 A14 PH4 A15 ADCLRC A16 ADCDAT A17 DACLRC A18 DACDAT A19 CODEC_BCLK A20 PF9 A21 XTO A23 GND B1 B2 B3 B4 B5 B6 B7 B8 B9 PG7 PG9 PG11 PG10 VDDINT GND PPIFS1/TMR0 PF1 PF3
E22 CMODE E23 LLINEIN F1 F2 PG3 BMODE1
F22 LOUT F23 RLINEIN G1 G2 G7 G8 PG1 BMODE0 VDDEXT VDDEXT VDDEXT
AA22 USB_DP AA23 USB_XO AB1 AB3 AB4 AB5 AB6 AB7 AB8 AB9 ADDR19 ADDR13 ADDR11 ADDR7 ADDR8 ADDR6 ADDR3 ADDR1 ABE0/SDQM0
VDDMEM N7
VDDMEM T7
VDDMEM AB2
A22 XTI/CODEC_MCLK G9
G10 VDDEXT G11 VDDEXT G12 VDDEXT G13 VDDEXT G14 VDDEXT G15 VDDEXT G16 HPVDD G17 HPGND G22 ROUT G23 VMID H1 H2 H7 H8 H9 PG2 PG0 VDDEXT VDDINT VDDINT
K10 GND K11 GND K12 GND K13 GND K14 GND K15 GND K16 VDDINT K17 VDDEXT K22 PH6 K23 PH5 L1 L2 L7 L8 L9 TCK TMS VDDINT GND
N10 GND N11 GND N12 GND N13 GND N14 GND N15 GND N16 VDDINT N17 VDDEXT N22 PH13 N23 PH14 P1 P2 P8 P9 DATA9 DATA10 VDDINT GND
T10 VDDINT T11 VDDINT T12 VDDINT T13 VDDINT T14 VDDINT T15 VDDINT T16 VDDINT T17 VDDEXT T22 GND T23 PH9 U1 U2 U8 U9 DATA5 DATA3
AB10 SWE AB11 VPPOTP AB12 SRAS AB13 SCKE AB14 AWE AB15 AMS3 AB16 AMS1
B10 PF5 B11 PF4 B12 PF6 B13 PF7 B14 PH3 B15 PF10 B16 PF8 B17 PF11
VDDMEM P7
VDDMEM U7
VDDMEM AB17 ARE VDDMEM AB18 CLKOUT VDDMEM AB19 CLKBUF
H10 VDDINT H11 VDDINT H12 VDDINT
L10 GND L11 GND L12 GND
P10 GND P11 GND P12 GND
U10 VDDMEM AB20 USB_VBUS U11 VDDMEM AB21 USB_DM U12 VDDMEM AB22 VRSEL
Rev. PrC |
Page 42 of 44 |
June 2008
Preliminary Technical Data
Ball Signal No. B18 PF12 B19 PF13 B20 LHPOUT B21 RHPOUT B22 SCL Ball Signal No. H13 VDDINT H14 VDDINT H15 VDDINT H16 VDDINT H17 VDDEXT Ball Signal No. L13 GND L14 GND L15 GND L16 VDDINT L17 VDDEXT
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Ball Signal No. P13 GND P14 GND P15 GND P16 VDDINT P17 VDDEXT Ball Signal No. Ball No. Signal Ball No. Signal
Table 41. 289-Ball Mini-BGA Ball Assignment (Numerically by Ball Number) (Continued)
U13 VDDMEM AB23 USB_XI U14 VDDMEM AC1 U15 VDDMEM AC2 U16 VDDMEM AC3 U17 VDDEXT AC4 GND ADDR14 ADDR12 ADDR10
Figure 36 shows the top view of the mini-BGA ball configuration. Figure 35 shows the bottom view of the mini-BGA ball configuration.
A1 BALL PAD CORNER A B C D E F G H J K L M N KEY: P R V DDINT GND AGND T U V V DDEXT I/O V DDMEM W Y AVDD HPVDD HPGND AA AB AC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 TOP VIEW
Figure 35. 289-Ball Mini-BGA Ball Configuration (Top View)
Rev. PrC |
Page 43 of 44 |
June 2008
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Preliminary Technical Data
A1 BALL PAD CORNER
A B C D E F G H J K L M N P R T U V W Y AA AB AC AVDD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BOTTOM VIEW 8 7 6 5 4 3 2 1 V DDEXT I/O HPVDD V DDMEM V DDINT GND AGND KEY:
HPGND
Figure 36. 289-Ball Mini-BGA Ball Configuration (Bottom View)
ORDERING GUIDE
Model Temperature Range1 Package Description Package Instruction Operating Voltage Option Rate (Max) (Nom) 600 MHz tbd V internal, 1.8 V or 3.3 V I/O
ADSP-BF527KBCZ6C1X 0C to +70C 289-Ball Chip Scale Package Ball Grid Array BC-289 (Mini-BGA)
1
Referenced temperature is ambient temperature.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06876-0-6/08(PrC)
Rev. PrC |
Page 44 of 44 |
June 2008

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